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PLBV46 to DCR

Product Description

The PLBV46 to DCR Bridge translates transactions received on its PLB interface into DCR master operations.Its design utilizes an PLB interface module to abstract PLB transactions into a simple SRAM style protocol that is easier to design with.

Key Features & Benefits

  • Connects as a 32-bit slave on PLB V4.6 buses of 32-bit, 64-bit, or 128-bit
  • 32-bit DCR master data width with a 10-bit DCR address bus
  • Memory-mapped interface from PLB to DCR, no special instructions required
  • Increased timing flexibility in typical systems where the PLB clock is slower than the CPU clock

Featured Documents

Tools and Device Support

Device Family Support:

Design Tools Support:

xilinx-131x43
  • License: Xilinx End User License Agreement

Featured Documents

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