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PLBv46 Endpoint Bridge for PCI Express

Product Description

The PLBv46 Endpoint is an interface between the Processor Local Bus (PLB) and the PCI Express (PCIe®) silicon hard core. The PLBv46 Endpoint sub-system provides full bridge functionality between the PLB bus architecture and the PCIe network. The sub-system is composed of the PCIe core, one GT interface and the PLBv46 Endpoint. The bridge circuit is implemented in the FPGA fabric and the PCIe core and GT are hard-core elements in the FPGA.

The PLBv46 Endpoint provides a transaction level translation of PLB bus commands to PCIe TLP packets and PCIe requests to PLB bus commands.

Key Features & Benefits

  • Endpoint only
  • Support PLB memory access to PCIe memory
  • Provide PLB master access for PCIe devices
  • Translate PLB transactions to appropriate PCIe
  • Transaction Layer Packets (TLP) packets
  • Track and Manage TLPs that require completion processing
  • Indicate error conditions detected by the PCIe core through interrupts
  • Supports up to 3 remote PLB memory regions mapped to PCIe address space
  • Address spaces are defined with a base address, an upper address, and an address translation value

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Tools and Device Support

Device Family Support:

Design Tools Support:

xilinx-131x43
  • Bundled With: Embedded Development Kit
  • License: Xilinx End User License Agreement

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