PLBV46 to PLBV46 Bridge

Documentation

• PLBv46 to PLBv46 Bridge

Device Family Support

• Virtex-5 FX
• Virtex-5 FXT
• Virtex-5 LX
• Virtex-5 LXT
• Virtex-5 SX
• Virtex-5 SXT
• Virtex-5 TXT
• Virtex-4
• Virtex-6
• Spartan-6

The PLBv46 (Processor Local Bus Version 4.6 with Xilinx simplification) to PLBv46 Bridge allows the designer to connect two PLB buses. The PLBv46 to PLBv46 Bridge can be used to isolate the slow PLB peripherals from the primary PLB and improve the system performance. The PLBv46 to PLBv46 Bridge is a slave on the primary PLB and is a master on the secondary PLB. The Xilinx PLBv46 to PLBv46 Bridge design allows customers to tailor the bridge to suit their application by setting certain parameters to enable/disable features.

Key Features

• Supports prefetching for read operations
• Supports posted writes to the slave
• Communicates with 32, 64, and 128 bit masters on primary PLB
• Communicates with 32, 64 and 128 bit slaves on Secondary PLB
• Supports 1:1, 2:1, and 4:1 clock frequency ratios from primary PLB to secondary PLB
• Interrupt service to identify abnormal terminations
• Exclusive resets to primary PLB and secondary PLB
• Supports burst of maximum 16 data beats