Processor System Reset Module
Bundled With:
Both EDK and Vivado
License:
Xilinx End User License
Program:
LogiCORE
Design Tools Support:
- ISE Design Suite
- IDS Embedded Edition
- Vivado Design Suite
Documentation
Device Family Support
- Artix-7
- Kintex-7
- Virtex-7
- Virtex-6
- Virtex-4
- Spartan-6
- Spartan-3A
- Spartan-3A DSP
- Spartan-3AN
- Zynq-7000
- Spartan-3E
- Spartan-3
The Xilinx Processor System Reset Module design allows the customer to tailor the design to suit their application by setting certain parameters to enable/disable features. The parameterizable features of the design are discussed in Processor System Reset Module Design Parameters.
Key Features
- Asynchronous external reset input is synchronized with clock.
- Asynchronous auxiliary external reset input is synchronized with clock.
- Both the external and auxiliary reset inputs are selectable active high or active low.
- Selectable minimum pulse width for reset inputs to be recognized.
- Selectable load equalizing.
- DCM Locked input.
- Power On Reset generation.