The RLD3 Controller gives you the ability to design for Reduced Latency DRAM while maintaining high performance and density. Build the RLD3 Controller with the Memory Interface GUI to get a complete set of unencrypted RTL, constraints, simulation files, and scripts.
Key Features and Benefits
- x9, x18, x36 device targets
- Up to 2.24Gb density
- Source code delivery in Verilog