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UltraScale Gen3 Integrated Block for PCI Express (PCIe)

Product Description

Xilinx provides a PCI Express Gen3 Integrated block for PCI Express® (PCIe) in the UltraScale™ family of FPGAs. The UltraScale FPGA solution for PCI Express Gen3 includes all of the necessary components to create a complete solution for PCIe.  Delivered through Vivado®, the Xilinx IP for Endpoint and Root Port simplifies the design process and reduces time-to-market.

This core combined with Xilinx Targeted Design Platforms, helps customers develop system solutions.

Recommended for:

  • High Peformance and High Bandwidth Applications
  • Compute and Data Co-processing Applications
  • Medical Imaging, High-Performance Computing & Communications Packet Processing

Deliver:

  • The Xilinx Integrated Block for PCIe is provided at no additional cost

Key Features & Benefits

  • Compliant with the PCI Express Base Specification 3.0
  • Supported Lane width: x1, x2, x4 and x8
  • Fully compliant with PCI Express transaction ordering rules
  • Optimal buffering for high bandwidth Direct Memory Access (DMA) applications
  • Bandwidth scalability interconnect width
  • AXI4-Stream Interface

Featured Documents

Tools and Device Support

Device Family Support:

Design Tools Support:

Related Products

xilinx-131x43
  • Bundled With: Vivado Design Suite
  • License: Xilinx End User License Agreement
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