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Virtex-5 Soft Error Mitigation (SEM) Core

 

Program:

LogiCORE

Documentation
Device Family Support
  • Virtex-5 FXT
  • Virtex-5 LX
  • Virtex-5 LXT

The Virtex®-5 Soft Error Mitigation (SEM) IP core performs both SEU detection and correction. The core utilizes Virtex-5 ICAP and ECC primitives to clock and observe the readback CRC circuit as part of the SEU detection function. For SEU detection, the IP core performs the necessary operations to locate and correct SEU errors using the Virtex-5 built-in ECC facility.

The Virtex-5 SEM IP core also performs emulation of SEUs within the Virtex-5 device by injecting errors in a controlled and predictable way into the configuration memory. It also provides a means to evaluate and test the readback CRC circuit and the error correction capabilities of the IP core which is impossible with real SEUs.

For test purposes, the connection to ICAP is used to facilitate the controlled injection of configuration errors.

The IP core is provided in both VHDL and Verilog HDL.

Key Features

  • Automatically detects and corrects SEU errors
  • Provides facility for error injection so all aspects of a system can be evaluated
  • Supports up to 60MHz clock. Default 50MHz
  • Functions as "Intelligent Sensor" that connects to the system
  • Includes simple UART interface to connect to either a terminal or embedded processor
  • Supports VHDL and Verilog
 
 
 
 
 
 
 
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