Video In to AXI4-Stream
AXI Interface Support:
- AXI4-Stream
Bundled With:
ISE
License:
Xilinx End User License
Program:
LogiCORE
Design Tools Support:
- Vivado Design Suite
- ISE Design Suite
Included at no additional charge with ISE software.
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Product Details
Documentation
Device Family Support
- Zynq-7000
- Artix-7
- Kintex-7
- Virtex-7
- Virtex-6 HXT
- Virtex-6 LXT
- Virtex-6 SXT
- Spartan-6 LX
- Spartan-6 LXT
Xilinx Video in to AXI4-Stream IP core enables video designers to quickly and easily connect external video signals to video processing blocks that use AXI4-Stream.
The Video In to AXI-4 Stream LogiCORE™ IP core converts common parallel video signals (such as from a DVI PHY) to an AXI4-Stream interface. The input video signals must have data, clock, DE, sync signals (Vsync and Hsync) and/or blanking signals (Vblank and Hblank). The AXI4-Stream interface signals are compliant to the AXI4-Stream Video Protocol as defined in the AXI Reference Guide (UG761), and as is implemented on most Xilinx Video IP cores. This enables video designers to quickly and easily connect an external video source to subsequent processing blocks that use a video protocol on the AXI4-Stream interface (such as Xilinx Video IP). This core works in conjunction with the Xilinx Video Timing Controller (VTC) core to detect characteristics of the incoming video format that can be read by a system processor and used to configure subsequent processing blocks. Source code is provided with the core to allow customers to adapt the core to work with unique video signals that may not already be included in the core.Key Features
- Configurable input data width accepts 8-64 bits enabling use with a variety of video source types and video data formats such as DVI, sub-sampled image sensor data, monochrome data, etc.
- AXI4-Stream interface is compliant with the AXI4-Stream Video Protocol as described in the AXI Reference Guide (UG761)
- Supports 1080P60 pixel clock rates in all supported devices families
- Supports 4kx2k at 24Hz clock rates in supported high performance devices
- Designed to operate in conjunction with the Xilinx Video Timing Controller IP Core
- Handles asynchronous clock boundary crossing between video clock domain and AXI4-Stream clock domain
Related Information
Related Products
| 1. What deliverables are are provided with the Video in to AXI4-Stream core? | ||
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| 2. What are the target applications for this product? | ||
Video and image processing applications in Aerospace and Defense, Automotive, Broadcast, Consumer, Industrial and Medical applications. | ||
| 3. What Xilinx FPGA families and speed grades does the Video in to AXI4-Stream core support? | ||
Please refer to the System Requirements Schedule for information on supported FPGA device families and speed grades. | ||
| 4. What is the availability, cost and licensing terms for the Video in to AXI4-Stream core? | ||
The Video in to AXI4-Stream core is available now. The core is included with Xilinx ISE software and entitles you to Xilinx world class technical support and access to any future update. Source code is included with the core to enable customers to modify the core to support other video signal configurations that may not be already included with the core. This core is provided under the terms of the Xilinx LogiCORE End User License Agreement. | ||
| 5. What are the FPGA resource requirements for the core, and are there any features that can be omitted to reduce this? | ||
Refer to the data sheet for detailed resource requirements. Resource requirements are dependent upon the option selected at synthesis time. | ||
| 6. Has the Video in to AXI4-Stream core been verified in hardware? | ||
Yes | ||
| 7. How can I evaluate the core | ||
The Video in to AXI4-Stream Core is included with ISE. No evaluation licensing is required. | ||
| 8. Where can I find a list of Known Issues? | ||
Xilinx IP Release Notes: xtp205 contains a complete listing of the current known issues for the core. |