XPS General Purpose IO
Bundled With:
EDK
License:
Xilinx End User License
Program:
LogiCORE
Design Tools Support:
- ISE Design Suite
Documentation
Device Family Support
- Virtex-6
- Virtex-5 FX
- Virtex-5 FXT
- Virtex-5 LX
- Virtex-5 LXT
- Virtex-5 SX
- Virtex-5 SXT
- Virtex-5 TXT
- Virtex-4
- Spartan-6
- Spartan-3A
- Spartan-3AN
- Spartan-3E
- Spartan-3
This document describes the specifications for the General Purpose Input/Output (GPIO) core for the Processor Local Bus (PLB). The XPS GPIO is a 32-bit peripheral that attaches to the PLB.
Key Features
- PLB interface is based on PLB v4.6 specification
- Configurable as single or dual GPIO channel(s)
- Number of GPIO bits configurable from 1 to 32 bits
- Each GPIO bit can be dynamically programmed as input or output
- Can be configured as inputs-only on a per channel basis to reduce resource utilization
- Ports for both 3-state and non 3-state connections