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XPS IIC Bus Interface

Product Description

Included in EDK at no additional charge starting in EDK9.2i

This product specification defines the architecture, hardware (signal) interface, software (register) interface and parameterization options for the XPS IIC module. It provides a low speed, two wire, serial bus interface to a large number of popular devices.

Key Features & Benefits

  • Master or slave operation
  • Multi-master operation
  • Software selectable acknowledge bit
  • Arbitration lost interrupt with automatic mode switching from master to slave.
  • Calling address identification interrupt with automatic mode switching from master to slave
  • START and STOP signal generation/detection
  • Repeated START signal generation
  • Acknowledge bit generation/detection
  • Bus busy detection
  • Fast mode 400 KHz operation or standard mode 100 KHz
  • 7 bit or 10 bit addressing
  • General call enable or disable
  • Transmit and receive FIFOs - 16 bytes deep
  • Throttling
  • General purpose output, 1 bit to 8 bits wide
  • Dynamic Start/Stop generation

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Tools and Device Support

Device Family Support:

Design Tools Support:

xilinx-131x43
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  • Bundled With: Embedded Development Kit
  • License: Xilinx End User License Agreement

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