UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Zynq UltraScale+ MPSoC Processing System IP

Xilinx provides the Processing System IP Wrapper for the Zynq UltraScale+ MPSoC to accelerate your design and its configuration for your embedded products

Product Description

The Processing System IP is the software interface around the Zynq® Ultrascale+™ MPSoC Processing System. The Zynq UltraScale MPSoC family consists of a system-on-chip (SoC) style integrated processing system (PS) and a Programmable Logic (PL) unit, providing an extensible and flexible SoC solution on a single die.

The Processing System IP Wrapper acts as a logic connection between the PS and the PL while assisting you to integrate custom and embedded IPs with the processing system using the Vivado® IP integrator.

Key Features & Benefits

  • Enable/Disable I/O Peripherals (IOP)
  • Enable/Disable AXI I/O ports (AIO)
  • MIO Configuration
  • Extended MULTIPLE USE I/Os (EMIO)
  • DDR Configuration
  • Security and Isolation Configuration
  • Interconnect logic for Vivado IP - PS interface
  • PL Clocks and Interrupts

Featured Documents

Tools and Device Support

Device Family Support:

Design Tools Support:

Related Products

xilinx-131x43
  • Bundled With: Vivado Design Suite
  • License: Xilinx End User License Agreement
Page Bookmarked