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Zynq Bus Functional Model (BFM)

The ability to purchase Zynq BFM has been discontinued as of December 1, 2016.  The existing AXI-BFM licenses will work perpetually in releases through 2016.4, but will not be supported after the Vivado 2016.4 release.

Zynq BFM will be replaced by Xilinx Zynq Verification IP in CY2017.  For more information please contact your Local Xilinx Sales Contact.

Product Description

The Zynq®-7000 SoC Bus Functional Model (BFM) supports the functional simulation of Zynq-7000 based applications. It is targeted to enable the functional verification of Programmable Logic (PL) by mimicking the PS-PL interfaces and OCM/DDR memories of Processor System (PS) logic. This BFM is delivered as a package of encrypted Verilog modules. BFM operation is controlled by using a sequence of Verilog tasks contained in a Verilog-syntax file.

Key Features and Benefits

  • Pin compatible and Verilog Based simulation model
  • Supports all AXI interfaces
  • AXI 3.0 compliant
  • Sparse memory model (for DDR) and a RAM model (for OCM)
  • Verilog task-based API
  • Delivered in Vivado® Design Suite
  • Blocking and non-blocking interrupt support
  • Requires license to AXI BFM models

There are no evaluation licenses for AXI BFM IP.


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