Product Details
Documentation
Device Family Support
- Spartan-3
- Spartan-3 XA
- Spartan-3A
- Spartan-3A DSP
- Spartan-3AN
- Virtex-4 LX
- Virtex-4 SX
- Virtex-4 XA
- Virtex-5 FX
- Virtex-5 FXT
- Virtex-5 LX
- Virtex-5 LXT
- Virtex-5 SXT
- Virtex-II
- Virtex-II Pro
Xilinx provides a flexible Block Memory Generator core to create compact, high-performance memories running at up to 450 MHz
The Block Memory Generator LogiCORE™ IP core automates the creation of area and performance optimized block memories for Xilinx FPGAs. Available through the ISE™ CORE Generator™ System, the core allows users to create block memory functions to suit a variety of requirements. Built-in knowledge about Xilinx device architectures allow it to leverage specialized FPGA architectural features to create the most compact, high performance solution.
A Migration Kit is available to automate the migration of Dual Port Block Memory and Single Port Block Memory LogiCORE IP to the newer Block Memory Generator style core.
Key Features
- Generates Single-Port RAM, Simple Dual-Port RAM, True Dual-Port RAM, Single-Port ROM, or Dual-Port ROM
- Performance up to 450 MHz
- Data widths from 1 to 1152 bits
- Memory depths from 8 to 9M (limited only by memory resources on target device)
- Variable port aspect ratios for dual-port configurations
- Variable Read-to-Write aspect ratios in Virtex-4 and Virtex-5 FPGAs
- Optimized algorithm for minimum block RAM resource utilization
- Configurable memory initialization values
- Supports individual write enable per byte in Spartan-3A, Spartan-3A DSP, Virtex-4 and Virtex-5 devices
- Separate output register controls for Port A and Port B
- Selectable per-port operating mode: WRITE_FIRST, READ_FIRST or NO_CHANGE
- VHDL and Verilog behavioral models optimized for fast simulation times
- Structural simulation model option for precise simulation of memory behaviors
