Cascaded Integrator Comb (CIC) Compiler

Product Details

• Release Notes (PDF)
• Ask Xilinx About this Core

Documentation

• Cascaded Integrator Comb (CIC) Compiler

Device Family Support

• Virtex-6
• Virtex-5
• Virtex-4
• Spartan-6
• Spartan-3A
• Spartan-3A DSP
• Spartan-3E
• Spartan-3

Requirements

• ISE 11.3 or higher
• ISE IP Updates 11.3 or higher

The Cascaded Integrator Comb (CIC) Filter, or Hogenauer filter, is a multiplierless filter architecture that is extremely important for implementing area efficient high sample rate changes in Digital Down Converters (DDC) and Digital Up Converters (DUC). Although its algorithm is quite easily understood, hardware engineers are looking to avoid the time consumed by implementing and maintaining their own IP, while also looking to be able to make quick, informed and resource efficient implementation decisions.

The CIC Compiler reduces filter implementation time to the push of a button, while also providing users with the ability to make trade-offs between differing hardware implementations of their CIC Filter specification. These easily made trade-offs give users the ability to select the most resource and power efficient solutions for their specific applications.

Finally, Virtex™-6 and Spartan™-6 performance reaches close to the 450 MHz (-1) and 250 MHz (-4) achievable, permitting support for the highest performance ADC and DAC technology available or alternatively supporting more channels in a single structure to save area.

New Features in v1.3

• Support added for Virtex-6 and Spartan-6 device families
• Support added for input and output streaming interface for multiple channel implementations
• Automatically shares resources when the core is over sampled
• Capability added to specify hardware over sampling specification as a sample period.
• Supports automatic CORE Generator™ update from CIC Compiler v1.1 and CIC Compiler v1.2

Key Features

• Performance reaching up to 450 MHz for Virtex-6 devices (-1 speed grade)
• Performance reaching up to 250 MHz for Spartan-6 devices (-2 speed grade)
• Support for typical algorithmic requirements: Interpolation and Decimation, three to six CIC stages, one or two differential delays.
• Fixed or programmable rate change from 4 to 8192
• Supports upto 16 channels
• Quick access to the filter frequency response enables algorithmic trade-offs between bit widths, stages, rate change, differential delay, rounding, to be made while also accessing the resource efficiency of the implementation.
• Implementation trade-offs between XtremeDSP^TM slice and Logic usage, enable users to achieve the correct balance of resources used and performance.
• For use with Xilinx CORE Generator™ and Xilinx System Generator for DSP™