Product Details
Documentation
Device Family Support
- Spartan-3 XA
- Spartan-3A
- Spartan-3A DSP
- Spartan-3E
- Virtex-4 FX
- Virtex-4 FX XA
- Spartan-3
- Virtex-4 LX
- Virtex-4 SX
- Virtex-5 FXT
- Virtex-5 LX
- Virtex-5 LXT
- Virtex-5 SXT
- Virtex-II Pro
Requirements
The Cascaded Integrator Comb (CIC) Filter, or Hogenauer filter, is a multiplierless filter architecture that is extremely important for implementing area efficient high sample rate changes in Digital Down Converters (DDC) and Digital Up Converters (DUC). Although its algorithm is quite easily understood, hardware engineers are looking to avoid the time consumed by implementing and maintaining their own IP, while also looking to be able to make quick, informed and resource efficient implementation decisions.
The CIC Compiler v1.2 reduces filter implementation time to the push of a button, while also providing users with the ability to make trade-offs between differing hardware implementations of their CIC Filter specification. These easily made trade-offs give users the ability to select the most resource and power efficient solutions for their specific applications.
Finally, Virtex™-5 and Spartan™-3A DSP performance reaches close to the 450 MHz (-1) and 250 MHz (-4) achievable, permitting support for the highest performance ADC and DAC technology available or alternatively supporting more channels in a single structure to save area.
Key Features
- Performance reaching up to the 450 MHz maximum performance of Virtex-5 (-1) Solutions.
- Performance reaching up to the 250 MHz maximum performance of Spartan-3A DSP (-4) Solutions.
- Performance reaching up to the 450 MHz maximum performance of Virtex-5 (-1) Solutions.
- Support for typical algorithmic requirements: fixed rate and programmable rate Interpolation and Decimation
- Quick access to the filter frequency response enables algorithmic trade-offs between bit widths, stages, rate change, differential delay, rounding, to be made while also accessing the resource efficiency of the implementation.
- Implementation trade-offs between DSP48 and Logic usage, enable users to achieve the correct balance of resources used and performance.
- Automatic control of hardware folding for the most compact implementation.
- Efficient multi-channel implementations and Hogenauer pruning significantly save resources
- Instantaneous Latency and Resource Estimation of DSP48/MULT18x18 and BRAM allows rapid comparison between key trade-offs.
