The CWda18 IP core is a configurable multi-channel audio interface component designed to input serial (TDM) digital audio streams from various manufacturers. The CWda18 can be configured at runtime to support an arbitrary number of audio channels (up to 128), and number of bits per sample: 8, 12, 16, 20, 24 and 32 bits. The CWda18 also supports the well known stereo formats: Philips I2S, Left-Justified or Right-Justified. The audio samples are retrieved from a receive FIFO where the channels are ordered and interleaved. A runtime configurable input stage de-serializes the serial audio stream and writes samples to the FIFO in the received order. The FIFO output is clocked with the core clock (cw_clk) unrelated to Fs (it must be clocked at a frequency above Number_of_Channels x Fs, where Fs is the sample rate frequency). The FIFO input is clocked with the serial audio clock (sclk or mclk) at a frequency Frame Period x Fs. The CWda18 IP core is supplied with either AMBA™ (CWda18a) or CW-Link (CWda18p) interface
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