Documentation
Device Family Support
- Virtex-4 FX
- Virtex-4 LX
- Virtex-4 SX
- Virtex-II Pro
- Virtex-II
- Virtex-E
- Virtex
- Spartan-IIE
The 32-bit Device Control Register Bus (DCR) IP core provides the DCR bus structure as described in the IBM 32-Bit Device Control Register Bus (DCR) Architecture Specification to allow easy connection of the DCR Master to the DCR slaves. It provides the daisy-chain for the DCR data bus and the OR gate for the DCR acknowledge signals from the DCR slaves.