DCR Interrupt Controller (DO-EDK)

Documentation

• DCR Interrupt Controller

Device Family Support

• Virtex-4 FX
• Virtex-4 LX
• Virtex-4 SX
• Virtex-II Pro
• Virtex-II
• Virtex-E
• Spartan-3
• Spartan-II
• Spartan-IIE

A DCR Interrupt Controller is composed of a bus-centric wrapper containing the IntC core and a DCR bus interface. The IntC core is a simple, parameterized interrupt controller that, along with the appropriate bus interface, attaches to either the OPB (On-chip Peripheral Bus) or the DCR (Device Control Register) bus.

Key Features

• Priority between interrupt requests is determined by vector position. The least significant bit (LSB, in this case bit 0) has the highest priority.
• Modular design provides core interrupt controller functionality instantiated within a bus interface design (currently OPB and DCR buses supported).
• DCR v2.0 bus interface.
• Supports address bus width of 10-bits and data bus width of 32-bits for DCR interface.
• Number of interrupt inputs is configurable up to the width of the data bus.