3GPP LTE UL Channel Decoder

Product Details

• Turbo Code Licensing Program

Documentation

• 3GPP LTE UL Channel Decoder

Device Family Support

• Virtex-6 HXT
• Virtex-6 CXT
• Virtex-6 LXT
• Virtex-6 SXT
• Virtex-5 FXT
• Virtex-5 LX
• Virtex-5 LXT
• Virtex-5 SXT
• Virtex-5 TXT
• Virtex-4 FX
• Virtex-4 LX
• Virtex-4 SX
• Spartan-6 LX
• Spartan-6 LXT
• Spartan-3A
• Spartan-3A DSP
• Spartan-3E
• Spartan-3

The 3GPP LTE Channel Decoder offers an optimized system level functional block to customers, saving significant development effort and resources.

The 3GPP LTE Channel Decoder performs the Physical Uplink Shared Channel (PUSCH) and Physical Uplink Control Channel (PUCCH) decoding operations as defined in the 3GPP-LTE standards. The LogiCORE™ IP accepts a demodulated bitstream from the preceding QAM demapper block and implements rate-dematching, LLR combining supporting H-ARQ processes, Turbo Decoding and transport block reassembly. A CRC check is finally applied, the result of which is sent to the higher-layer control plane for the management of H-ARQ retransmission requests. The 3GPP LTE Channel Decoder represents a key component in Xilinx LTE Baseband Targeted Design Platform.

Key Features

• Implements the PUSCH and PUCCH channel decode functions
• Designed according to the 3GPP 36.212 v8.5 specifications
• Includes the LTE Turbo Decoder and Viterbi Decoder LogiCores, also available as a stand-alone products
• Scalable from high throughput multiple codeword eNBs to Femtocells
• Supports HARQ combining
• Bit accurate C model available