Generic Framing Procedure (DO-DI-GFP)

Part Number:

EF-DI-GFP-SITE

License:

SignOnce

Product Type:

Core

Program:

LogiCORE

Product Details
Device Family Support
  • Virtex-5 LX
  • Virtex-5 FXT
  • Virtex-5 LXT
  • Virtex-5 SXT
  • Virtex-5 TXT
  • Virtex-4 FX
  • Virtex-4 LX
  • Virtex-4 SX
  • Virtex-II Pro
  • Virtex-II
  • Spartan-3E
  • Spartan-3

Please note that this core is discontinued as of July 31, 2009 and is no longer orderable

The Xilinx GFP core solution fully implements the International Telecommunication Union’s Generic Framing Procedure recommendation (G.7041/Y.1303). All protocols defined by the ITU’s Telecommunication Standardization Sector (ITU-T) are supported, including Ethernet, PPP, RPR, GE, Fibre Channel, FICON, ESCON, and DVB-ASI. The GFP core includes the capability to perform end-to-end frame delineation, and supports both client management and data frames. The GFP core can be configured for frame-mapped, transparent, or mixed-mode operation on a per-channel basis, enabling multi-line, multi-service cards and systems in Ethernet-over-SONET or Data-over-SONET applications.

Key Features

  • Fully compliant with ITU-T G.7041 GFP recommendation
  • Supports frame-mapped, transparent, and mixed-mode operation
  • Supports both null and linear frames, enabling one to ten unique channels
  • Enables multi-line/multi-protocol MSPP's, i.e. 10x 1-GE => OC-192
  • Individually optimized for OC-48 or OC-192 applications
  • Supports both client data frames and client management frames
  • Supports dynamic reconfiguration, error insertion, and status monitoring via host interface
  • Separate MAP and UNMAP cores support unique ingress/egress path requirements
  • Utilizes Xilinx standard LocalLink interface for easy integration
  • Fully configurable using the Xilinx CORE Generator tools
 

In addition to supporting all of the features specified by G.7041, the Xilinx GFP solution provides options to facilitate system-level integration and debugging such as error injection on a per-frame basis for all scrambling and CRC functions. With the Xilinx CORE Generator™ tool, the GFP core can be easily configured to support specific system requirements, including individually optimized cores for OC-48 and OC-192 applications. The GFP core is quickly integrated into design environments using Xilinx’s standard LocalLink interface, and operational modes can be controlled through the optional host interface.

 
 
 
 
 
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