Product Details
Device Family Support
- Spartan-3
- Spartan-3E
- Virtex-4 FX
- Virtex-4 LX
- Virtex-4 SX
- Virtex-5 LX
- Virtex-5 LXT
- Virtex-5 SXT
- Virtex-II
- Virtex-II Pro
- Spartan-3A DSP
Requirements
- ISE 9.2i Service Pack 2 or higher
- ISE 9.2i IP Update 2
The Xilinx® SPI-3 Physical (PHY) Layer core provides a fully compliant Packet over SONET (POS) solution, which can be quickly integrated into networking systems. Through user-configurable options, such as interface width, internal Tx and Rx FIFOs, and byte or packet-level transfers, the SPI-3 core provides design flexibility while seamlessly interoperating with industry leading Application Specific Standard Products (ASSPs) to maximize the data transfer bandwidth. The Xilinx SPI-3 core is fully compliant with the Optical Internetworking Forums System Packet Interface Level 3 (SPI-3) standard (OIF-SPI3-01.0), as well as the SATURN® Development Groups POS-PHY Level 3 (PL3) interface specification.
Key Features
- Fully compliant with OIF-SPI3-01.0 System Packet Interface Level-3 (SPI-3) standard
- Aggregate bandwidth in excess of 2.5-Gbps supporting OC-48 line rates and beyond
- Configurable interface data widths: 32-bit, 16-bit, and 8-bit
- Byte-Level and Packet-Level Transmit flow control options
- Supports 1 to 256 addressable channels
- Transmit and Receive cores are delivered as independent solutions for flexible implementation
- Fully parameterizable internal FIFO using BlockRAM, Distributed Memory, or built-in FIFO primitives
- Configurable Transmit Calendar implementation
- LocalLink User Interface allows easy interconnection
The SPI-3 PHY Layer core connects to Link layer devices within networking applications. The core communicates between devices using the SPI-3 interface standard at up to 5.6-Gbps, enabling OC-48 POS, ATM, and Gb Ethernet applications. The Xilinx SPI-3 PHY layer core has been verified in hardware to interoperate with the Intel IXP2400 Network Processor.
