RapidIO Logical (I/O) and Transport Layer Interface Core

Product Details

• RapidIO Basics
• RapidIO & DSP Solution
• RapidIO Testimonials
• Ask Xilinx About this Core

Documentation

• RapidIO Logical (I/O) and Transport Layer Interface Core
• Release Notes (PDF)
• Xilinx Core Site License (PDF)

Device Family Support

• Virtex-6 LXT
• Virtex-6 SXT
• Virtex-5 FXT
• Virtex-5 LXT
• Virtex-5 SXT
• Virtex-4 FX

The RapidIO Logical (I/O) and Transport Layer Interface is optimized for Virtex®-5 LXT/SXT/FXT, Virtex-4FX and Virtex-II Pro series FPGAs and is compliant with Logical Input/Output and Common Transport Specification 1.3. With the Xilinx LogiCORE RapidIO Logical (I/O) and Transport layer interface, a designer can build a customized, fully compliant system with the highest possible sustained performance of 10 Gbits/sec per direction over 4 lanes. Combining the Xilinx RapidIO Logical (I/O) and Transport Layer Interface core with a Xilinx RapidIO Physical Layer core provide all layers required to implement a RapidIO endpoint.

The RapidIO architecture is an electronic data communications standard for interconnecting microprocessors, DSPs, communications and network processors, system memory, and peripheral devices on a circuit board and several such circuit boards using a backplane. It is a packet-switched point-to-point technology used for passing data and control information within embedded systems, primarily used in networking and communications equipment.

Key Features

• Implements Rev 1.3 of the RapidIO Input/Output Logical and Common Transport Layer Specification
• Supports concurrent Initiator and Target operations
• 64-bit internal data path
• Dedicated port for Maintenance transactions
• Six separate User ports with independent data flow control, includes two Maintenance ports that can interface with the Xilinx Register Manager or a User defined module
• Supports an aggregate data throughput of 10 Gb/s in each direction
• Simple handshaking mechanism to control data flow
• Door bell and message support