Product Details
Documentation
Device Family Support
- Virtex-5 FXT
- Virtex-4 FX
- Virtex-5 LXT
- Virtex-5 SXT
- Virtex-II Pro
Requirements
The RapidIO Physical Layer Interface, is a fixed netlist solution for the RapidIO interconnect, is a fully compliant, pre-implemented and fully tested module for Xilinx Virtex™-5 LXT/SXT/FXT, Virtex-4 FX and Virtex-II Pro series FPGAs. This core was designed to ensure predictable timing thereby significantly reducing engineering time and allowing resources to be focused on unique user application logic in the FPGA and on the system-level design. Combining the Xilinx RapidIO Logical (I/O) and Transport Layer Interface core with a Xilinx RapidIO Physical Layer core provide all layers required to implement a RapidIO endpoint.The RapidIO architecture is an electronic data communications standard for interconnecting microprocessors, DSPs, communications and network processors, system memory, and peripheral devices on a circuit board and several such circuit boards using a backplane. It is a packet-switched point-to-point technology used for passing data and control information within embedded systems, primarily used in networking and communications equipment.
Key Features
- 1x & 4x Serial PHY - Supports Virtex-5 LXT/SXT/FXT, Virtex-4 FX and Virtex-II Pro FPGAs
- 1x & 4x Serial PHY - Supports 1.25, 2.5, and 3.125 Gpbs line speed
- 1x & 4x Serial PHY - 64-bit internal data path
- Supports Packet Retry, stomp, transmission error recovery, throttle-based flow control and CRC
- Dynamic clock phasing alignment
