RapidIO Physical Layer Interface Core

Product Details

• RapidIO Basics
• RapidIO & DSP Solution
• RapidIO Testimonials
• Ask Xilinx About this Core

Documentation

• RapidIO Physical Layer Interface Core
• Release Notes (PDF)
• Xilinx Core Site License (PDF)

Device Family Support

• Virtex-6 SXT
• Virtex-5 FXT
• Virtex-5 LXT
• Virtex-5 SXT
• Virtex-4 FX
• Virtex-6 LXT

Requirements

The LogiCORE™ IP RapidIO Physical Layer Interface core, a fixed netlist solution for the RapidIO interconnect, is fully compliant, pre-implemented and tested module for the Virtex®-5 LXT/SXT/FXT, Virtex-4 FX and Virtex-II Pro series FPGAs. This core is designed to ensure predictable timing, thereby significantly reducing engineering time investment and allowing resources to be focused on user-specific application logic.

The RapidIO Logical (I/O) and transport Layer core and the RapidIO Physical Layer core provide a complete Serial RapidIO protocol stack. Additionally, a highly optimized and configurable buffer design is included with these cores to implement a Serial RapidIO endpoint. While a modular IP design approach provides flexibility to enable ease of customization, the Xilinx tool chain automates generation of the serial endpoint on an FPGA by using these building block IP cores through a configurable and easy-to-use graphical user interface.

Key Features

• 1x & 4x Serial PHY - Supports Virtex-5 LXT/SXT/FXT, Virtex-4 FX and Virtex-II Pro FPGAs
• 1x & 4x Serial PHY - Supports 1.25, 2.5, and 3.125 Gpbs line speed
• 1x & 4x Serial PHY - 64-bit internal data path
• Supports Packet Retry, stomp, transmission error recovery, throttle-based flow control and CRC
• Dynamic clock phasing alignment