Data Side On Chip Memory
Documentation
Device Family Support
- Virtex-4 FX
- Virtex-4 LX
- Virtex-4 SX
- Virtex-II Pro
The DSOCM_V1.0 core is a data-side On-Chip Memory (OCM) bus interconnect core. The core connects the PowerPC405 data-side OCM interface to OCM peripherals, such as the data-side BRAM controller (DSBRAM_IF_CNTRL).
Key Features
- Designed for use with the DSBRAM_IF_CNTRL peripheral to provide a deterministic data-side BRAM memory solution for PowerPC405 based embedded systems.
- Delivered with the Embedded Development Kit.
- Single master - no bus arbitration logic.
- Configurable multiple slave capability - contains read-data multiplexing when used with 2 or more slaves.