OPB 10/100 Ethernet Media Access Controller (EMAC)

Xilinx bundles the following three configurations of the 10/100 Ethernet MAC together as its 10/100 Ethernet MAC solution.

• OPB (Peripheral Bus) 10/100 Ethernet MAC
• OPB 10/100 Ethernet MAC Lite
• PLB (Processor Local Bus) 10/100 Ethernet MAC

When you purchase the 10/100 Ethernet MAC product you will receive:

• a copy of the EDK, which contains all three of the cores listed above, and
• instructions on generating a FULL license for each of the three core configurations. This will allow you to generate the cores.

IPIF components:

• IPIF-Slave Attachment
• IPIF-Master Attachment
• IPIF-Address Decode
• IPIF-Interrupt Control
• IPIF-Read Packet FIFO
• IPIF-Write Packet FIFO
• IPIF-DMA (optional)
• IPIF-Scatter / Gather (optional)

• Simulation Models
• VHDL and Verilog design flow support
• Layer 0 and Layer 1 Device Drivers
• VxWorks RTOS Adaptation Layer (non-Lite core only)

10/100 Ethernet MAC Features:

The Xilinx 10/100 Ethernet MAC LogiCORE™ has been designed to the IEEE Std. 802.3 MII interface specification and support the following features:

• 32-bit OPB master and slave interfaces (OPB 10/100 EMAC and OPB 10/100 EMAC Lite)
• Memory mapped direct I/O interface to registers and FIFOs
• Media Independent Interface (MII) for connection to external 10/100 Mbps PHY transceivers
  • Designed to IEEE 802.3
  • Supports auto-negotiable and non auto-negotiable PHYs
  • Supports 10BASE-T and 100BASE-TX/FX IEEE 802.3 compliant MII PHYs at full or half duplex
• Independent internal 2K byte TX and RX FIFOs for storing data for more than one packet
• 16 entry deep FIFOs for Transmit Length, Receive Length, and Transmit Status registers to support multiple packet operation
• CSMA/CD compliant operation at 10 Mbps and 100 Mbps in half duplex mode
• Programmable PHY reset signal
• Internal loop-back capability
• Supports unicast, multicast, and broadcast transmit and receive modes as well as promiscuous address receive mode
• Supports a "Freeze" (graceful halt) mode based on input signal assertion to assist with emulator based software development
• Provides auto or manual source address field insertion or overwrite for transmission
• Provides auto or manual pad and Frame Check Sequence (FCS) field insertion
• Supports MII management control writes and reads with MII PHYs
• Programmable interframe gap

In addition, the "non-Lite", full featured 10/100 Ethernet MAC also supports:

• DMA and Scatter/Gather DMA capabilities for low processor and bus utilization
• Counters and interrupts for many error conditions

• MII (PHY side, built-in)
• RMII (PHY side, shim core)

The OPB 10/100 EMAC, OPB 10/100 EMAC Lite, and PLB 10/100 EMAC cores support the MII interface on the PHY side

RMII interface support can also be added by attaching an MII to RMII shim core to the EMAC to interface to PHYs that support this reduced pinout interface. The MII to RMII shim core is a free core which is bundled with EDK starting with EDK v3.2.

OPB:

The OPB 10/100 EMAC and EMAC Lite cores support the IBM On-Chip Peripheral Bus (OPB) interface on the processor side.

PLB:

If there are no other on-chip peripheral bus components you can save resources by using the PLB 10/100 Ethernet MAC configuration.

Using the PLB 10/100 Ethernet MAC gives you the opportunity to offload the OPB in systems which have a large number of OPB components. The PLB 10/100 core is also useful if you need to connect to the PLB and its associated control and data paths.

Datasheets for both configurations are accessible from the 10/100 EMAC product page.

The latest version of the core is supported by EDK v6.1 SP2 or later revision of Xilinx ISE v6.1i software.

To use the core, you must:

• Install the latest release of Xilinx EDK. The OPB and PLB 10/100 Ethernet MACs and the OPB10/100 Ethernet MAC Lite are distributed in Evaluation mode as part of the Xilinx EDK
  • Updates to EDK 6.x, including Service Packs, are available at: http://www.xilinx.com/edk/
• You must install the Xilinx ISE 6.1i and the ISE 6.1i Service Pack compatible with your installation of EDK. ISE is required to run the EDK (Embedded Development Kit) tools, which in turn allow you to configure the core.
  
  Updates to ISE 6.1ii including Service Packs are available at: http://support.xilinx.com/support/techsup/sw_updates

The following cores are sold together as Xilinx 10/100 Ethernet MAC Solution package and are available today:

• OPB (Peripheral Bus) 10/100 Ethernet MAC
• OPB 10/100 Ethernet MAC Lite
• PLB (Processor Local Bus) 10/100 Ethernet MAC

The 10/100 Ethernet MAC Solution is sold with a site license, which allows you to access the core and any additional updates that are provided for it for a period of one year from the date of purchase. Licensing information, instructions for downloading the core, as well as information on other related Xilinx IP products can be found on the product page for this core. The Xilinx 10/100 EMAC solution sells for $4995 US.

Please refer to Xilinx Answer 17124 for a more complete explanation of the differences between the 10/100 EMAC and 10/100 EMAC Lite cores.

The Upper and Lower limits of resource utilization range for the OPB 10/100 EMAC core is as follows:

For the OPB Ethernet MAC Lite core, the Upper and Lower limits of resource utilization is as follows:

Actual resource utilization will vary depending on features selected.

Please see the OPB 10/100 EMAC and OPB 10/100 EMAC Lite datasheets for a more detailed breakdown of resource utilization vs. feature selection.

Yes. The following features may be modified or omitted when customizing the 10/100 EMAC (non-Lite) core via the CORE Generator™ to reduce logic resource utilization:

• Interrupt Device ID Encoder may be omitted
• DMA support is optional. Users may choose between Simple DMA plus IPIF or support for Scatter/Gather DMA
• Half Duplex support may be omitted
• IPIF Packet FIFO depth may be reduced
• MAC length and Status FIFO depth can be reduced
• Module Identification Read (MIR) may be omitted
• Source Address Insertion may be omitted
• Error Status Counters may be omitted
• Software Reset Support may be omitted

The core has been designed to be compatible with industry standard PHYs with MII interfaces. The following PHYs have been tested with the 10/100 EMAC:

• Intel LXT970A
• Intel LXT971A
• Broadcom BCM5221
• National DP83861VQM

Third party IEEE 802.3 hardware conformance testing on the 10/100 Ethernet MAC was successfully completed at the University of New Hampshire Interoperability Lab (UNH IOL) on March 11, 2004. The Insight Electronics Virtex-II™ MB1000 development board supplemented with a P160 communications module was used as the test platform.

Contact your FAE to request a copy of the test reports.

Currently you must generate the core with either an OPB or PLB interface. In both cases installation of EDK is required.

In a future release the core will be enhanced so that it can be generated standalone without an OPB or PLB interface. For information on availability of a standalone core (with no OPB or PLB interface), please contact your FAE with details of your feature requirements.

All three cores are distributed with a built-in Full System Hardware Evaluation license in the appropriate Xilinx EDK (Embedded Development Kit) Service Pack release.

The built-in Full System Evaluation License allows you to try out the EMAC customization interface, generate the core, integrate it into your design, and process your design all the way through bitstream generation. You can also use the generated bitstream to program a Xilinx FPGA and evaluate the core in hardware. The evaluation core also allows you to generate a gate level Simprim library model which you can use to functionally simulate the core in your system.

Click on on the Evaluation Options link on the 10/100 EMAC Product page for information on the required Xilinx EDK and ISE software and Service Pack levels needed to perform this full system evaluation of the 10/100 EMAC in hardware.