FIFO Generator
Bundled With:
ISE
License:
Xilinx End User License
Product Type:
Core
Program:
LogiCORE
The FIFO Generator is included at no additional change with Xilinx ISE software
Product Details
Documentation
Device Family Support
- Virtex-6 -1L
- Virtex-6 HXT
- Virtex-6 LXT
- Virtex-6 SXT
- Virtex-5 FXT
- Virtex-5 LX
- Virtex-5 LXT
- Virtex-5 SXT
- Virtex-5 TXT
- Virtex-4 FX
- Virtex-4 LX
- Virtex-4 SX
- Virtex-4 XA
- Virtex-II Pro
- Virtex-II
- Virtex-E
- Virtex
- Spartan-6 LX
- Spartan-6 LXT
- Spartan-3A
- Spartan-3A DSP
- Spartan-3AN
- Spartan-3E
- Spartan-3 XA
- Spartan-3
- Spartan-II
- Spartan-IIE
The FIFO Generator core is a fully verified first-in, first-out (FIFO) memory queue ideal for applications requiring in-order data storage and retrieval. The core offers expanded functionality over the Asynchronous and Synchronous FIFO LogiCORE™ IP cores and should be used in all new designs wherever a FIFO function is required.
The parameterized core is delivered through the ISE® CORE Generator™ software. It is optimized to deliver maximum performance (up to 500 MHz) with minimal resource utilization. User-customizable settings for width, depth, status flags, memory type, and write/read port aspect ratios, as well as optional support for First Word Fall Through (FWFT) provide ample flexibility to support a wide range of design requirements.
A Migration Guide is available to provide guidance on how to migrate existing designs containing Synchronous FIFO v5.x and Asynchronous FIFO v6.x LogiCORE IP cores to this newer FIFO Generator style core.
Key Features
- FIFO depths up to 4,194,304 words
- FIFO data widths from 1 to 1024 bits
- Non-symmetric aspect ratios (read-to-write port ratios ranging from 1:8 to 8:1)
- Independent or common clock domains
- Selectable memory type (block RAM, distributed RAM, shift register, or built-in FIFO)
- Synchronous or asynchronous reset option
- Hamming Error Injection and Correction Checking (ECC) for built-in and block RAM FIFO
- First-word fall-through (FWFT)
- Full and empty status flags, and almost full and almost empty flags for indicating one-word-left
- Programmable full and empty status flags, set by user-defined constant(s) or dedicated input port(s)
- Configurable handshake signals • Embedded register option for block RAM and built-in FIFO
- Fully configurable using the Xilinx CORE. Auto-update feature available in CORE Generator to convert older versions of the Block Memory Generator core to the latest