AES Fast Encryptor and Decryptor (Helion)
Device Family Support
- Virtex-6
- Virtex-5
- Virtex-4
- Spartan-6
- Spartan-3A
- Spartan-3A DSP
- Spartan-3AN
- Spartan-3A XA
- Spartan-3E
- Spartan-3
The Helion AES cores implement the FIPS-specified AES algorithm. Two main functions are available, encryption and decryption, and are offered separately for optimum flexibility. The encryptor core accepts a 128-bit plaintext input block, and generates a corresponding 128-bit ciphertext output block using a supplied 128-, 192-, or 256-bit AES key. The decryptor core provides the reverse function, generating plaintext from supplied ciphertext, using a similar AES key as was used for encryption.
Key Features
- Implements AES (Rijndael) to latest NIST FIPS PUB 197.
- Full dynamic support for all AES key sizes (128, 192 and 256-bits).
- Designed especially for high data throughput applications.
- Lower and higher rate versions also available.
- Configurable for full duplex operation or resource shared half duplex operation.
- Fully FIPS certified.
- Available to support all modes of AES.
- Highly optimized for Xilinx FPGAs.
Target Markets
- Broadcast
- Aerospace & Defense
- Data Processing & Storage
- Industrial/Scientific/Medical
- Wired Communications
- Wireless Communications
Device Implementation Matrix
Device utilization metrics for example implementations of this core. Contact provider for more information.
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