Interlaken is a scalable chip-to-chip interconnect protocol designed to enable transmission speeds from 10Gbps to 100Gbps and beyond. Using the latest SERDES technology and a flexible protocol layer, Interlaken minimizes the pin and power overhead of chip-to-chip interconnect and provides a scalable solution that can be used throughout an entire system. In addition, Interlaken uses two levels of CRC checking and a self-synchronizing data scrambler to ensure data integrity and link robustness. Sarance’s Interlaken IP Core (IIPC) is delivered as a netlist targeted at a specific FPGA architecture. The IIPC is compliant with the Interlaken Protocol Definition, Revision 1.1, and offers system designers with a risk-free and quick path for adopting Interlaken as their chip-to-chip interconnect protocol.
Key Features
- Support for up to 50 Gbps of throughput
- Programmable BurstMax, BurstMin, BurstShort and MetaFrameSize parameters
- Data striping and de-striping across 1 to 24 lanes (limited by FPGA I/O resources)
- Support for Synchronization, Scrambler State, Diagnostic, and Skip Word Block Types
- Data scrambling and disparity tracking to minimize baseline wander and maintain DC balance
- Channel-level and link-level flow control mechanism
- Full error checking and recovery as defined by Interlaken specification
