The OPB BRAM Interface Controller is a module that attaches to the OPB (On-chip Peripheral Bus). It also serves as the interface between between the OPB and the bram_block peripheral. A BRAM memory subsystem consists of the controller along with the actual BRAM components that are included in the bram_block peripheral. The core is parameterizable and can be customized for a specific embedded application in Xilinx FPGAs. This IP core is one of more than 20 IP cores that are part of the Embedded Development Kit.
Key Features
- Supports a wide range of memory sizes
- Supports OPB v2.0 byte-enable architecture
- Interface between OPB and bram_block