OPB IIC Master and Slave Bus Controller
Bundled With:
EDK
License:
Xilinx End User License
Product Type:
Core
Program:
LogiCORE
Included in EDK at no additional charge starting in EDK9.2i
Documentation
Device Family Support
- Virtex-4 FX
- Virtex-4 LX
- Virtex-4 SX
- Virtex-II Pro
- Virtex-II
- Virtex-E
- Virtex
- Spartan-3A
- Spartan-3
- Spartan-IIE
Requirements
EDK 9.2i
ISE™ 9.2 SP1 or later
The IIC bus interface soft IP core communicates with other devices on the OPB (On-Chip Peripheral Bus). It includes the Master and Slave Controller and supports the following features: Master or Slave operation, multi-master operation, software selectable acknowledge bit, arbitration lost interrupt with automatic mode switching from Master to Slave, calling address identification interrupt with automatic mode switching from Master to Slave. The core supports all features specified in the Philips IIC specification v2.1, except the high-speed mode. The IIC core can be parameterized for customer specific applications.
Key Features
- Plug and play with other processor IP cores from Xilinx
- Generate MicroBlaze™ based embedded system in the Xilinx® FPGAs
- Parameterizable to customer needs
- Provides communication with other cores on the OPB