OPB IPIF Architecture
Bundled With:
EDK
Product Type:
Core
Program:
LogiCORE
Documentation
Device Family Support
- Virtex-4 LX
- Virtex-4 SX
- Virtex-II Pro
- Virtex-II
- Virtex-E
- Virtex
- Spartan-3A
- Spartan-3E
- Spartan-3
- Spartan-IIE
- Virtex-4 FX
The OPB IPIF architecture specification facilitates the connection of Xilinx or customer IP modules to the IBM On-Chip Peripheral Bus (OPB). The OPB is part of IBM's CoreConnect™ family of data buses and associated infrastructure. CoreConnect is intended for use in system-on-chip environments, including XIlinx Virtex-II Pro™ FPGAs with embedded PowerPC™ hard processors and FPGAs using the MicroBlaze™ soft processor. This IP core is one of more than 20 IP cores that are part of the Embedded Development Kit.
Key Features
- One of the infrastructure cores available in the Embedded Development Kit (EDK)