PLB BRAM Controller

Product Details

• Ask Xilinx About this Core

Documentation

• PLB BRAM Controller

Device Family Support

• Virtex-II Pro
• Virtex-4 FX

The PLB BRAM Interface Controller is a module that attaches to the PLB (Processor Local Bus) and is an interface with between the PLB and the bram_block peripheral. A BRAM memory subsystem consists of the controller along with the actual BRAM components that are included in the bram_block peripheral. This controller supports the PLB v3.4 byte enable architecture and supports a wide range of memory sizes. This IP core is one of more than 20 IP cores that are part of the Embedded Development Kit.

Key Features

• Handles byte, half-word, word and double word transfers
• Used to design high-performance embedded systems using PowerPC in Virtex-II Pro
• Interface between PLB bus and the BRAM memory