PLB Gigabit Ethernet Media Access Controller (PLB GEMAC)

The PLB Gigabit Ethernet MAC has a 64-bit Processor Local Bus (PLB) backend interface which can be used to connect the MAC with the PowerPC™ in Virtex-II Pro™.

The PowerPC core is integrated into the Virtex-II Pro FPGA using the IP-Immersion architecture, which allows hard IP cores to be diffused at any location deep inside the FPGA fabric, while maintaining unprecedented connectivity with the surrounding FPGA fabric.

The Processor Local Bus (PLB) is part of the IBM-developed CoreConnect™ on-chip bus communications link which provides separate 32-bit address and 64-bit data buses for instruction and data.

The following features are included with the PLB GEMAC core:

• IPIF-Slave Attachment
• IPIF-Master Attachment
• IPIF-Address Decode
• IPIF-Interrupt Control
• IPIF-Read Packet FIFO
• IPIF-Write Packet FIFO
• Simulation Models
• VHDL and Verilog integration support
• OS-independent Device Drivers
• VxWorks Adaptation Layer
• Device Test Code
• Full Duplex Only

The PLB GEMAC is configured using the Embedded Development Kit (EDK) therefore a valid EDK v6.1 license is required to generate the core. ISE v6.1i SP3 or a later Service Pack version of this software is required for place and route of the core.

EDK is an all-encompassing solution for designing embedded programmable systems. EDK supports the design of processor sub-systems using the IBM PowerPC™ hard processor core as well as the Xilinx MicroBlaze™ soft processor core.

The non-PLB Gigabit Ethernet MAC core does not require EDK.

The standard driver for the PLB GEMAC core is a Layer 1 driver. Layer 1 drivers are typically used in embedded systems marketed without an RTOS. The standard PLB GEMAC Layer 1 driver can be used with an RTOS, but it does not tightly integrate with the network stack of the RTOS automatically.

Currently Xilinx offers the following driver support for the PLB GEMAC core:

Linux driver support for MontaVista is currently under development and scheduled for release by Monta Vista in 2QCY04 as part of Monta Vista's Professional Edition offering. Contact Monta Vista for details.

The documentation on Layer 0 and 1 driver support for the various Xilinx processor related cores can be found in the EDK Device Driver documentation:

/ise/embedded/xilinx_drivers.pdf

General instructions on accessing VxWorks adapters can be found
in the Processor IP Reference Guide, specifically the chapter on
"Automatic Generation of Tornado 2.x (VxWorks 5.x) Board Support Packages".

The PLB Gigabit Ethernet MAC core is compatible with the same PHYs that are compatible with the standard Gigabit Ethernet MAC core.

The Stratos Lightwave RJK-ST11 and R14K-ST11 Optical Transceivers have been tested with the non-PLB core.

After you have purchased and installed the Embedded Development Kit, a simple IP Evaluation Lounge registration is required to obtain a three month Full System Evaluation license. The Full System Evaluation license will allow you to parameterize, generate, and instantiate the PLB Gigabit Ethernet MAC core in your design. You can place and route your design, create a bitstream and use it to program a Xilinx FPGA device so that you can verify the core's functionality in hardware.

For more information, go to the Processor Peripheral IP Evaluation page.

The PLB GEMAC core is part of the Xilinx Platform FPGA SystemIO solution, which addresses all aspects of system connectivity in high-performance designs. Xilinx provides the most comprehensive Ethernet MAC offerings in the programmable industry. In addition to PLB GEMAC core, Xilinx also provides a XAUI standalone core, a 1 Gb Ethernet MAC core with a choice of GMII interface, 1000BASE-X PCS with Ten Bit Interface, or integrated 1000BASE-X PCS/PMA, a 10 Gb Ethernet MAC, an Ethernet 1000BASE-X PCS/PMA core, as well as a 10/100 Ethernet MAC core with choice of OPB or PLB interface for embedded MicroBlaze™ and PowerPC solutions.

Click here for a complete listing of Xilinx Ethernet IP solutions.