PLB GPIO

Product Details

• Ask Xilinx About this Core

Documentation

• PLB GPIO

Device Family Support

• Virtex-II
• Virtex-II Pro
• Virtex-4 FX

Requirements

The General-Purpose Input/Output (GPIO) module is a 32-bit peripheral that attaches to the Processor Local Bus (PLB). It supports 32-bit, 16-bit, and 8-bit bus interfaces. Each GPIO bit is dynamically programmable as input or output. A number of GPIO bits are configurable up to size of data bus interface and can be configured as inputs-only to reduce resource utilization. This IP core is one of more than 20 IP cores that are part of the Embedded Development Kit.

Key Features

• Configurable as single or dual GPIO channel(s).
• PLB v34 bus interface with byte-enable support.
• Optional interrupt request generation.
• Independent reset values for each bit of all registers.