PLB SDRAM Controller

Product Details

• Ask Xilinx About this Core

Documentation

• PLB SDRAM Controller

Device Family Support

• Virtex-II Pro
• Virtex-4 FX

The PLB SDRAM controller provides a SDRAM controller that connects to the PLB bus and provides the control interface for SDRAMs. The core offers designers the following features: PLB interface that can be used to perform device initialization sequence upon power-up and reset conditions, auto-refresh cycles. The core also supports single-beat and burst transactions, target-word first cache-line transactions, cacheline latencies of 2 or 3 set by a design parameter and various SDRAM data widths set by a design parameter. This IP core is one of more than 20 IP cores that are part of the Embedded Development Kit.

Key Features

• Used to design high-performance embedded systems using PowerPC core in Virtex-II Pro FPGAs
• Parameterizable to specific customer needs and application
• Connects to the PLB bus and provides control interface for SDRAMs