UltraController II
Click on Access Lounge to download the UltraController-II reference design.
Documentation
- UltraController II Product Brief (PDF)
- UltraController II QuickStart Tutorial - PROM Loading for Virtex-4 (PDF)
- UltraController II QuickStart Tutorial - PROM Loading Virtex-II Pro (PDF)
- UltraController II QuickStart Tutorial for Virtex-II Pro (PDF)
- UltraController QuickStart Tutorial (PDF)
- UltraController II QuickStart Tutorial for Virtex-4 (PDF)
Device Family Support
- Virtex-4 FX
- Virtex-II Pro
Meeting customer demand for enhanced capabilities, the UltraController II reference design increases performance while innovating on many aspects of the widely used UltraController. By using the UltraController II reference design, designers can leverage the immersed PowerPC™ 405 core in the Virtex™-4 FX and Virtex-II Pro family of devices to achieve maximum performance. The new UltraController II reference design provides designers with a general purpose controller that executes out of cache. Thirty-two bit general purpose input/outputs are provided which require no Block RAM, so virtually no logic resources are used. The UltraController II maintains the same ease of use established by the original UltraController design. Preconfigured and self contained, users download the UltraController II source code and use standard familiar design flows to compile, code, and debug their design: ISE™ for configuration bitstream and Xilinx Platform Studio (XPS)/EDK for software development. Software modifications are easily accomplished, users simply update their code base using XPS and recompile without any changes to the UltraController II hardware. Free download of the Verilog and VHDL source code for UltraController II is available including Quick Start tutorial guide and detailed application note.
Key Features
- Utilizes the PowerPC(s) in the Virtex-II Pro and Virtex-4 FX
- Compact, general-purpose controller utilizing only 10 logic cells
- Runs at up to 400 MHz in Virtex-II Pro and 450 MHz in Virtex-4 FX
- Execute and load code using the integrated 16 KB instruction and 16 KB data caches
- 32-bit input and 32-bit output ports can interface with logic internal or external to the FPGA without BRAM
- External interrupt support
- Timer functionality support (FIT, PIT, Watchdog)
- Easy to integrate using the standard Xilinx ISE/Platform Studio tool flow
- Verilog and VHDL source code provided