Viterbi Decoder

Product Details

• Viterbi Synchronization Design Note (PDF)
• Block Decoding App Note (PDF)
• Ask Xilinx About this Core

Documentation

• Viterbi Decoder

Device Family Support

• Virtex-6 LX
• Virtex-6 LXT
• Virtex-5 FXT
• Virtex-5 LX
• Virtex-5 LXT
• Virtex-5 SXT
• Virtex-4 FX
• Virtex-4 LX
• Virtex-4 SX
• Virtex-II Pro
• Virtex-II
• Virtex
• Spartan-6 LX
• Spartan-6 LXT
• Spartan-3A
• Spartan-3A DSP
• Spartan-3E
• Spartan-3

Viterbi Decoders are used in systems where data are transmitted and subject to errors before reception. Compatible with many common standards such as DVB, 3GPP2, IEEE802.16, HiperLAN, Intelsat IESS-308/309, the Viterbi Decoder LogiCORE™ IP, along with other forward error correction cores from Xilinx offers highly-flexible concatenated codecs. The Viterbi Decoder LogiCORE IP consists of two basic architectures: a fully parallel implementation which gives fast data throughput and a serial implementation which occupies a small area. The core also has a puncturing option, giving a large range of transmission rates and reducing the bandwidth requirement on the channel. Puncturing can also be carried out externally to the decoder and the erasure pins in the erasure bus ERASE can be asserted to indicate the presence of null-symbols.

Key Features

• High-speed, compact Viterbi Decoder.
• Two architectural options (parallel or serial) allow user to optimize for throughput or resource utilization.
• Very low latency option.
• Parameterizable constraint length, convolution codes, traceback length and soft data width.
• Decoder rates from 1/2 to 1/7.
• Supports multi-channel applications.
• Compatible Encoder core available in Xilinx CORE Generator™.