PLB to OPB Bridge

Documentation

• PLB to OPB Bridge

Device Family Support

• Virtex-II
• Virtex-4 FX
• Virtex-II Pro
• Virtex-E
• Virtex
• Spartan-3
• Spartan-IIE
• Spartan

The On-Chip Peripheral Bus (OPB) to Processor Local Bus (PLB) Bridge module translates OPB transactions into PLB transactions. It functions as a slave on the OPB side and a master on the PLB side. Access to the control register and bus error status registers is user selectable from either the OPB or an optional DCR interface. The OPB to PLB Bridge is necessary in systems where an OPB master device, such as a DMA engine or an OPB based coprocessor, requires access to PLB devices (i.e. high speed memory devices, etc.).

Key Features

• 64-bit PLB Master interface and communicates with 32- or 64-bit PLB slaves
• Translates OPB sequential accesses (bursts) to either cacheline or fixed length PLB burst transfers
• Supports a code block length variable up to 4095 symbols with up to 256 check symbols
• 32-bit OPB Slave interface with byte enable transfers
• Allows customers to tailor the bridge to suit their application by setting certain parameters to enable / disable features