PLB EMC (DO-EDK)

Product Details

• Ask Xilinx About this Core

Documentation

• PLB EMC

Device Family Support

• Virtex-II Pro
• Virtex-II
• Virtex-4 FX

This IP module supports data transfers between the Processor Local Bus (PLB) and external synchronous and asynchronous memory devices. Example synchronous devices for use with this controller are the synchronous Integrated Device Technology, Inc. IDT71V546 SRAM with ZBT ™ Feature. Example asynchro-nous devices include the IDT71V416S SRAM and Intel 28F128J3A StrataFlash Memory. The Xilinx EMC design allows the customer to tailor the EMC to suit their application by setting certain parameters to enable/disable features.

Key Features

• Parameterized for up to a total of eight memory (Synchronous/Asynchronous) banks
• Separate Control Register for each bank of memory to control memory mode
• Memory width is independent of PLB bus width (memory width must be less than or equal to PLB bus width)