The PLB IPIF is a CoreConnect compatible LogiCORE ™ that provides a bi-directional interface between a User IP core and the PLB 64-bit bus standard. The PLB is the local bus for the Embedded PPC405 processor featured in the Xilinx Virtex™ II Pro products.
Key Features
- Compatible with IBM CoreConnect 64-bit PLB
- Supports User IP data widths from 8 bits to 64 bits with automatic byte steering
- DMA function with optional Scatter/Gather mechanization.
- Extensive User customizing support via HDL parameterization.