PLB RAPIDIO LVDS Design

Product Details

• Ask Xilinx About this Core

Device Family Support

• Virtex-II Pro

The Xilinx PLB RapidIO™ LVDS Intellectual Property (IP) solution is a LOGICCORE™ module that provides an interface between the IBM ® CoreConnect™ Processor Local Bus (PLB) and an LVDS based RapidIO interface standard. The PLB RapidIO LVDS design provides an interface between the PPC405 (via PLB CoreConnect Bus) and a RapidIO protocol network. The physical interface to the RapidIO bus uses the 8 bit LVDS standard.

Key Features

• Front end Interface to the IBM CoreConnect PLB Bus
• Back end Interface to RapidIO Bus
• Processor Accessible Registers
• System Interrupt Support
• PLB System clock frequency up to 100 MHz
• Provides for user interface tailoring via 16 input parameters.