Processor System Reset Module

Documentation

• Processor System Reset Module (v2.00a)

Device Family Support

• Virtex-II Pro
• Virtex-II
• Virtex-4 FX
• Virtex-E
• Virtex
• Spartan-II
• Spartan-IIE

The Xilinx Processor System Reset Module design allows the customer to tailor the design to suit their application by setting certain parameters to enable/disable features. The parameterizable features of the design are discussed in Processor System Reset Module Design Parameters.

Key Features

• Asynchronous external reset input is synchronized with clock.
• Asynchronous auxiliary external reset input is synchronized with clock.
• Both the external and auxiliary reset inputs are selectable active high or active low.
• Selectable minimum pulse width for reset inputs to be recognized.
• Selectable load equalizing.
• DCM Locked input.
• Power On Reset generation.