Product Details
Documentation
Device Family Support
- Spartan-3A
- Spartan-3A DSP
- Spartan-3AN
- Virtex-4 FX
- Virtex-4 LX
- Virtex-4 SX
- Virtex-5 LX
- Virtex-5 LXT
- Virtex-5 SXT
XPS_LL_TEMAC Ethernet core provides a control interface to internal registers via a 32-bit Processor Local Bus (PLB) Version 4.6 as described in the IBM CoreConnect™ 128-Bit Processor Local Bus, Architectural Specification Version 4.6. This PLB slave interface supports single beat read and write data transfers (no burst transfers).
TEMAC is an acronym for Tri-Mode Ethernet Media Access Controller and is a reference to the three speed (10, 100, and 1000 Mb/S) capable Ethernet MAC function available in this core.
The XPS_LL_TEMAC core supports both the Xilinx hard silicon Ethernet MAC in Virtex-5 FXT, LXT, and SXT and Virtex-4 FX devices as well as a soft Ethernet MAC option for these and other supported devices.
This core has been designed to IEEE Std. 802.3-2002.The hard silicon TEMAC configurations of this core are included with EDK at no additional cost, while the soft TEMAC configurations are separately licensed.
Key Features
- Independent 2K, 4K, 8K, 16K, or 32K Byte TX and RX data FIFOs for queueing frames
- Filtering of "bad" receive frames
- Support for several PHY interfaces
- Media Independent Interface Management access to PHY registers
- Full Duplex operation
- Optional support for jumbo frames up to 9K Bytes
- Optional TX and RX TCP/UDP partial checksum off load in hardware
- Support for VLAN frames
- Support for Pause frames for flow control
- Auto PAD and FCS field stripping or pass through on receive
- One or two full duplex Ethernet bus interfaces with a shared control interface and independent data and interrupt interfaces
