Single Event Upsets

Single-Event Upsets (SEUs) are random, unintentional changes in the state of memory cells and can affect ASICs, ASSPs, and FPGAs. For over a decade, Xilinx has been enhancing its architecture and technology to minimize and mitigate the effects of SEUs, enabling customers to meet their system-level, Failure-in-Time (FIT) budgets. As a result, Xilinx FPGAs are among the most reliable and best characterized of any integrated circuits. Xilinx has achieved the best FIT rate in the industry, and such low upset rates intrinsically satisfy the reliability requirements for many applications. Xilinx also offers free IP for the most advanced protection against SEUs.

• Terrestrial FIT rate of approximately 100 FIT/Mb of configuration memory for the Xilinx 7 series FPGAs.
• Extensive research and development leading to over 50 patents.
• Xilinx is the only company that publishes SEU test data (PDF) and has been doing so for over ten years.

With every generation, Xilinx continues its tradition of innovation in architecture and testing to minimize and mitigate SEU effects, including:

• Process technology
• Circuit layout
• Device architecture
• Software libraries
• Software tools
• Documentation

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  FIT Reduction Methods in 7 Series FPGAs

  
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Xilinx offers automatic detect and correct circuitry (CRC/ECC) (PDF) with Partial Reconfiguration.

• Scans and corrects 2-bit upsets in 20-30ms for most devices
• Enables SEU logging and tracking
• CRC/ECC operates independently of user design

Xilinx offers advanced Soft Error Mitigation IP and Error Classification for increased availability.

• Enables prioritized reaction for errors more likely to affect design functionality
• Eliminates an average of 70% of soft errors as a source of concern
• Enables SEU simulation with upset injection feature

Xilinx offers Triple Modular Redundancy (TMR) through partners.

• Xilinx partners with Mentor enabling their Precision Hi-Rel synthesis software
• Xilinx offers TMRTool software for Space and other extreme reliability applications

Xilinx offers a wide spectrum of solutions to meet even the toughest of application requirements.

Hardened Configuration Protection

From Virtex®-5 onward, all Xilinx FPGAs offer continuous configuration error detection with the Readback CRC. Virtex-6 and all 7 series devices offer hardened error correction in addition to correction with the Frame_ECC as well. Details on Readback CRC and Frame_ECC can be found in the device configuration user guide.

In addition BRAM is protected by integrating error correction coding (ECC) support for user memory. You can find further information regarding the SEU mitigation features for specific devices by following the links below.

Devices

Xilinx offers many FPGAs with built in SEU detection and correction:

• 7 series FPGAs
• Virtex-6 FPGAs

Xilinx offers devices that support SEU detection (Correction supported with soft IP):

• Virtex-5 FPGAs
• Virtex-4 FPGAs
• Spartan®-6 FPGAs
• Extended Spartan-3A FPGA Families

Xilinx also offers radiation hardened devices with immunity to nuetron induced SEU:

• Virtex-5 QV FPGAs