DualEDGE Flip-Flop
The DualEDGE Flip-Flop capability increases the effective synchronous operation rate of any design up to the bandwidth limits of the device. In other words, you can operate any sequential design twice as fast for a given clock rate, or do the same amount of processing for 1/2 the external clock frequency.
- Distributes divided clock globally then double locally at macrocell
- Use 2x clocking for double data rate applications
- No additional insertion delay
- Available in all CoolRunner-II CPLDs
Figure 1: DualEDGE flip-flops allow for clocking on both edges
