XA CoolRunner-II CPLD Family

Enhanced design security

Only CoolRunner-II CPLDs provide an unprecedented four levels of design security that guard against pattern theft.

• Designs can be secured during programming to prevent either overwriting or pattern theft via readback
• Electrical or visual detection of configuration patterns is eliminated with four new levels of on-chip security
• Electrical or laser tampering causes the device to automatically lock down
• Protection is buried deeply within the device making it virtually undetectable
• CoolRunner-II in Secure Applications (PDF)
• How CoolRunner-II CPLDs Protect FPGA IP (PDF)

DataGATE signal blocking

The CoolRunner-II architecture, with its all-digital core, requires far less power than the older CPLD technologies that use power-hungry analog sense amplifiers.

• Permits input signal blocking, stops input switching, and reduces power.
• Power management (duty cycle, clock input and input pin)
• Block input pins during insertion with hot plugging
• Block sections of logic and snapshot signals with latches through debugging
• Improve security by blocking access for various on stored code inside the device
• Employ the features of FZP technology to further advanced CoolRunner-II CPLDs as the low power standard
• DataGATE enables CoolRunner-II to be a small fraction of the system power consumption -- no other CPLD can do this!

Figure 1

DataGATE Dramatically Extends Battery Life

Multiple I/O banking

The CoolRunner-II advanced I/O interface capability fully addresses all aspects of system connectivity in a wide range of product applications.

• Enable easy communication between two distinct signal level interfaces
  • Including different bus interface I/O voltage levels
  • Voltage translation of peripheral devices
  • Memory to microcontrollers
  • Communication between wired interfaces
  • CoolRunner-II I/O Characteristics (PDF)

Figure 1

Multiple system integration is now available with CoolRunner-II CPLDs

Input hysteresis and programmable grounds

nput hysteresis provides designers with a tool to minimize external components. Whether using the inputs to create a clock, or reducing the need for external buffers to sharpen up an input signal, CoolRunner-II CPLD inputs provide designers with a flexible and powerful features:

• Improved noise immunity
• Reduced power consumption
• Superior signal integrity

Figure 1

Hysteresis (Schmitt trigger) input.

Clock Divider

Clock Divider improves power savings by providing clock division at standard values. CoolRunner-II CPLDs give the designer unsurpassed clock management features that enable an easy to implement total clock management solution.

• Gives solid clock division without using macrocells
• Duty cycle improvement
• Available in large densities (128 macrocells and above)
• Very low lag ...typically 50 ps!

Clock Doubler

The Clock Doubler enhances performance by doubling the internal clock speed. It is selectable for each macrocell and is ideal for Double Data Rate (DDR) memory devices.

• Doubles internal clock speed up to 400 MHz
• Available for each macrocell

CoolCLOCK

CoolCLOCK is a combination clock divider and clock doubler that divides the incoming clock by two and then doubles the clock at the output level to maintain the same performance while reducing the internal power consumption.

• Combines clock divider and doubler
• Divides incoming clock by 2
• Reduces overall clocking power

DualEDGE Flip-Flop

The DualEDGE Flip-Flop capability increases the effective synchronous operation rate of any design up to the bandwidth limits of the device. In other words, you can operate any sequential design twice as fast for a given clock rate, or do the same amount of processing for 1/2 the external clock frequency.

• Distributes divided clock globally then double locally at macrocell
• Use 2x clocking for double data rate applications
• No additional insertion delay
• Available in all CoolRunner-II CPLDs

Multiple LVCMOS, HSTL, SSTL I/O

You can easily create standard chip-to-chip and chip-to-memory interfaces and thus remove discrete interface devices from your system. This saves you money and increases your system reliability.

• LVTTL and LVCMOS for standard chip-to-chip interfacing
• SSTL and HSTL for standard chip-to-memory interfacing

Figure 1

I/O Performance and Flexibility (*1.5V inputs need hysteresis.)

Small form factor packaging

Xilinx leads the way in advanced package innovation by offering two new, ultra small form-factor, Quad Flat no-lead (QF) packages to the popular full line-up of Chip Scale Packages (CP).

• Maximum board space savings
• Lower cost QF32 package only requires 25mm2 of board space
• Simplifies board routing and allowing smaller overall end-products
• Perfect for handheld and other space constrained applications that need 32 or 64 macrocell CPLDs in the smallest possible space.

CoolRunner-II offers the newest 0.5mm pitch QF and CP packages for the broadest selection of low cost, small form-factor packages at 1.8 volts from 21 to 117 I/O.

Figure 1

The QF32, CP56, QF48 and CP132 CoolRunner-II packages are required for portable, ASIC fix & other size constrained applications

Table 1

CPLD package options (Max I/O is listed in parenthesis)