Built on the state-of-the-art 28nm HPL process technology, the 7 Series All Programmable FPGA family delivers breakout performance, capacity, and system integration while optimizing price/performance/watt. Learn more about how Xilinx is delivering a generation ahead at 28nm and staying a generation ahead at 20nm.
| Value | Deliverables |
|---|---|
| Programmable Systems Integration |
|
| Increased System Performance |
|
| BOM Cost Reduction |
|
| Total Power Reduction |
|
| Accelerated Design Productivity |
|
| Features | Artix-7 | Kintex-7 | Virtex-7 | Spartan-6 | Virtex-6 |
|---|---|---|---|---|---|
| Logic Cells | 215,000 | 480,000 | 2,000,000 | 150,000 | 760,000 |
| BlockRAM | 13Mb | 34Mb | 68Mb | 4.8Mb | 38Mb |
| DSP Slices | 740 | 1,920 | 3,600 | 180 | 2,016 |
| DSP Performance (symmetric FIR) | 930GMACs | 2,845GMACs | 5,335GMACs | 140GMACs | 2,419GMACs |
| Transceiver Count | 16 | 32 | 96 | 8 | 72 |
| Transceiver Speed | 6.6Gb/s | 12.5Gb/s | 28.05Gb/s | 3.2Gb/s | 11.18Gb/s |
| Total Transceiver Bandwidth (full duplex) | 211Gb/s | 800Gb/s | 2,784Gb/s | 50Gb/s | 536Gb/s |
| Memory Interface (DDR3) | 1,066Mb/s | 1,866Mb/s | 1,866Mb/s | 800Mb/s | 1,066Mb/s |
| PCI Express® Interface | x4 Gen2 | x8 Gen2 | x8 Gen3 | x1 Gen1 | x8 Gen2 |
| Analog Mixed Signal (AMS)/XADC | Yes | Yes | Yes | Yes | |
| Configuration AES | Yes | Yes | Yes | Yes | Yes |
| I/O Pins | 500 | 500 | 1,200 | 576 | 1,200 |
| I/O Voltage | 1.2V, 1.35V, 1.5V, 1.8V, 2.5V, 3.3V | 1.2V, 1.35V, 1.5V, 1.8V, 2.5V, 3.3V | 1.2V, 1.35V, 1.5V, 1.8V, 2.5V, 3.3V | 1.2V, 1.5V, 1.8V, 2.5V, 3.3V | 1.2V, 1.5V, 1.8V, 2.5V |
| EasyPath Cost Reduction Solution | - | Yes | Yes | - | Yes |