The Spartan-6 family of FPGAs offer low-risk, more efficient dual-register 6-input look-up tables (LUT)s by leveraging the CLB structure first introduced with the Virtex-5 FPGA family.

• Efficient 6-input LUTs improve performance and minimize power
• LUT designed with dual flip-flops for pipelined centric applications
• Flexible LUTs are configurable as logic, distributed RAM or shift registers
• From 3,400 to 150,000 logic cells for greater system-level integration

Each Spartan-6 FPGA provides abundant clock lines to address the different clocking requirements of high fanout, short propagation delay, and extremely low skew.

• Low noise, flexible clocking
• Digital Clock Managers (DCMs) eliminate clock skew and duty cycle distortion
• Phase-Locked Loops (PLLs) for low‑jitter clocking
• Frequency synthesis with simultaneous multiplication, division, and phase shifting
• 16 low-skew global clock networks

The Spartan-6 FPGA family increases block RAM size with higher memory to logic ratio than previous generations. All Spartan-6 FPGA devices have between 12 and 268 dual-port block RAMs, each storing 18Kbits.

• Increased memory block capacity to 4.8Mbits
• Fast block RAM with byte write enable
• 18Kb blocks that can be optionally programmed as two independent 9Kb block RAMs
• Each block RAM has 2 completely independent ports that share stored data
  • Each port can be configured as 16K × 1, 8K × 2, 4K × 4, 2K × 9 (or 8), 1K × 18 (or 16), or 512 x 36 (or 32)

Dedicated memory controller blocks (MCB)s target a single-chip DRAM and support access rates of up to 800Mbps.

• DDR, DDR2, DDR3, and LPDDR support
• Data rates up to 800Mbps (12.8Gbps peak bandwidth)
• Internal 32-, 64-, or 128-bit data interface provides simple and reliable interface to the MCB
• Multi-port bus structure with independent FIFO to reduce design timing issues
• Predictable timing for memory interface designs
• Software wizard to guide through the entire process

Each I/O pin is configurable and can comply with a large number of standards, using up to 3.3V.

• Up to 1050Mbps data transfer rate per differential I/O
• Selectable output drive, up to 24mA per pin
• 3.3V to 1.2V I/O standards and protocols
  • Full 16mA and 24mA output drives
• Low‑cost HSTL and SSTL memory interfaces
• Hot swap compliance
• Adjustable I/O slew rates to improve signal integrity

Spartan-6 FPGAs contain dedicated, full-custom, low-power DSP slices, combining high speed with small size, while retaining system design flexibility.

• Up to 180 efficient, second generation DSP48A1 slices
• High-performance arithmetic and signal processing
• Each slice containing a fast 18 x 18 multiplier and a 48-bit accumulator capable of operating at 390MHz speed
• Pipelining and cascading capability
• Pre-adder to assist filter applications
• 50% lower power consumption: 1.38mW/ 100MHz at a 38% toggle rate

Each GTP transceiver is a combined transmitter and receiver capable of operating at a data rate between 600Mbps and 3.2Gbps.

• Implement serial protocols at lowest power
• Devices contain up to 8 gigabit transceiver circuits
• Up to 3.2Gbps performance
• High speed interfaces: Serial ATA, Aurora, 1G Ethernet, PCI Express, OBSAI, CPRI, EPON, GPON, DisplayPort, and XAUI
• Lower power consumption: < 150mW (typical) at 3.2Gbps
• Available in Spartan-6 LXT FPGA devices

Implemented in 45nm low-power technology, the Spartan-6 integrated end-point block for PCI Express 1.1 is low-risk and standards-compliant.

• Works with GTP transceivers to deliver PCIe® endpoint and root port function
• Built-in hard IP frees user logic resources and reduces power
• PCI SIG®-verified Gen1 compliance (on integrators list)
• Low cost PCI™ technology support compatible with the 32 bit, 66MHz specification
• Available in Spartan-6 LXT FPGA devices

The MicroBlaze soft processor solution gives you the flexibility to select a combination of peripherals, memory, and interface features you need at the lowest cost on a single FPGA.

• New MicroBlaze 7.0 adds MMU & FPU for greater functionality
• 6-input LUT architecture improves performance & efficiency for comparator & multiplexer
• 2X flip-flops for embedded registers
• Hard DRAM memory controller with 12.8Gbps memory bandwidth

Spartan-6 power management modes allow the devices to go to an extremely low power state reducing power consumption significantly.

• Up to 50% lower static power and 40% lower dynamic power
• Hibernate power‑down mode for zero power
• Suspend mode maintains state and configuration with multi-pin wake‑up, control enhancement
• Lower-power 1.0V core voltage (LX FPGAs, -1L only)
• High performance 1.2V core voltage (LX and LXT FPGAs, -2 and -3 speed grades)

Spartan-6 FPGAs include a unique, factory-programmed Device DNA identifier useful for tracking purposes, anticloning designs, or IP protection.

• Simplified configuration, supports low-cost standards
• 2-pin auto-detect configuration
• Broad third-party SPI (up to x4) and NOR Flash support
• Feature rich Xilinx Platform Flash with JTAG
• MultiBoot support for remote upgrade with multiple bitstreams, using watchdog protection
• Unique Device DNA identifier for design authentication
• AES bitstream encryption in the larger devices