• CLB is optimized for area and speed for compact high performance design.
• Four slices per CLB implement any combinatorial and sequential circuit.
• Each slice has 4-input look-up tables (LUT), flip-flops, multiplexors, arithmetic logic, carry logic, and dedicated internal routing.
• Dedicated AND/OR logic implements wide input functions.

Virtex-4 FPGAs incorporate advanced clocking capabilities that help you to achieve highest performance by minimizing clock jitter, skew, and duty cycle distortion.

• Abundant clock resources
  • 32 clock inputs (differential or single-ended)
  • 32 global clock networks
  • 16-48 regional clock networks
  • 8-24 distinct clock regions
  Abundant clock management features
  • Up to 20 Digital Clock Managers (DCMs)
  • Up to 8 Phase Matched Clock Dividers (PMCDs)
  • 32 Global Clock Buffers
  High Performance
  • 500 MHz clocking throughout the chip
  • 30% reduction in jitter
  • Automatic duty cycle precision
  Easy design
  • Quadrant and buffer restrictions eliminated
  • Enhanced Clocking Wizard for design generation
  • New automatic jitter and skew reporting for timing budgets
  Digital Clock Managers (DCM)
  • Clock deskew
  • Delay-locked loop (DLL) completely eliminates clock distribution delays
  Phase shift control
  • Coarse (quadrature) phase shifting
  • Fixed and variable fine-grained phase (1/256 clock period) shifting modes for clock/data synchronization
  • Direct DCM phase-shift control for advanced applications
  Flexible frequency generation from 24 MHz to 500 MHz
  • Integer multiplication and division parameters
  Dynamic reconfiguration of DCM multiply, divide, and phase shift
  • Two performance modes
  • Maximum Speed - maximum frequency, minimum jitter
  • Maximum Range - minimum frequency, widest phase shift range, lowest power
  Phase-Matched Clock Dividers (PMCD)
• A Virtex-4 clock management enhancement, PMCDs provide improved handling of multiple synchronous clock domains.
• Phase-matched divided clocks
  • Create up to four frequency-divided and phase-matched versions of an input clock
  • Divide by 1, 2, 4 or 8
  • Divided clocks are rising-edge aligned
  Phase-matched delayed clocks
  • Preserve edge alignments and phase relations between the divided clocks and other clocks
  Global Clock Buffers
  • Fully differential buffering and routing
  • Fully flexible programming
  • Use as a buffer or a mux
  • Use for synchronous or asynchronous switching
  • Optional tri-state enables
  • Optional clock enables

Shift Register SRL16 block

• Configure any CLB Look-Up Table (LUT) to work as a fast, compact, 16-bit shift register.
• Cascade LUTs to build longer shift registers.
• Implement pipeline registers and buffers for video, wireless.

Up to 1.36 Mbit Distributed RAM

• Configure any LUT to work as a single-port or dual-port 16-bit RAM/ROM.
• Cascade LUTs to build larger memories.
• Applications include flexible memory sizes, FIFOs, and buffers.

Up to 10 Mb Embedded Block RAM

• Up to 552 blocks of cascadable, synchronous 18 Kb block RAM.
• Configure any 18 Kb block as a single/dual-port RAM.
• Supports multiple aspect ratios, data-width conversion, and parity.
• Applications include data caches, deep FIFOs, and buffers.

High-Speed Memory Interfaces

• ChipSync™, SmartRAM, and Xesium clocking technologies make it easy to interface to the latest high-speed memories.

• New ChipSync source-synchronous technology simplifies board design
• 1 + Gbps differential I/O
• 600 Mbps single-ended I/O
• Digitally controlled impedeance with XCITE technology for reduced component count and board size

Virtex®-4 FX FPGAs include built-in Ethernet connectivity with up to four Ethernet media access controller (MAC) blocks. The Xilinx unique tri-mode Ethernet MAC provides guaranteed performance and UNH-verified interoperability. This integrated functionality reduces total system cost by reducing design and verification effort, freeing approximately 1,800 logic cells per Ethernet MAC in the FPGA fabric. Plus reduced component count, and simpler board design.

Features at a Glance

• Up to four Tri-mode Ethernet MACs per device.
• IEEE 802.3 compliant.
• Tri-mode EMAC - 10/100 Mbps mode, 1000 Mbps mode, 10/100/1000 Mbps mode.
• Programmable PHY Interface (MII, GMII, RGMII,SGMII).
• Seamless connection to RocketIO™ multi-gigabit transceivers.
• Saves up to 1800 logic cells per MAC.
• Receive address filter to accept/reject packets.
• Real Time Statistics for Transmit/Receive.
• Use with or without PowerPC® core.
• Great for Network Management or Remote FPGA Monitoring.
• Complete single-chip solution for 1000 Base-X when used RocketIO transceivers.

The Virtex-4 FX platform FPGAs provides up to two PowerPC® 405, 32-bit RISC processor cores in a single device. These industry standard processors offer high performance and a broad range of third-party support. The new Auxiliary Processor Unit (APU) controller simplifies the integration of hardware accelerators and co-processors.

Embedded PowerPC 405 (PPC405) core

• Embedded 450 MHz, 700+ DMIPS RISC core (32-bit Harvard architecture).
• 5-stage data path pipeline.
• Hardware multiply and divide.
• 32 x 32-bit general-purpose registers.
• 16 KB 2-way set-associative instruction and data caches.
• Memory Management Unit (MMU) enables RTOS implementation.
• 64-entry unified Translation Look-aside Buffers (TLB).
• Variable page sizes (1KB - 16 KB).
• Enhanced instruction and data On-Chip Memory (OCM) controllers interface directly to embedded Block RAM.
• Supports IBM CoreConnect bus architecture.
• Debug and trace support.

New Auxiliary Processor Unit (APU) controller interfaces the CPU pipeline directly to the FPGA fabric

• Enables Hardware Accelerators.
• Supports User Defined Instructions.
• Supports up to four 32-bit word data transfers in a single instruction.
• Floating point and co-processor support.
• Supports autonomous instructions: no pipeline stalls.
• 32-bit instruction and 64-bit data.
• 4-cycle cache line transfer.

Provides direct interface to Tri-mode Ethernet MAC configuration registers

• DSP Slices have been custom designed in silicon to achieve 500 MHz performance independently or when combined together within a column to implement DSP functions.
• Each DSP Slice draws only 2.3 mW/100 MHz, at a typical toggle rate of 38%, just 6% of the power consumption of previous FPGA DSP implementations.
• The DSP Slice supports over 40 dynamically controlled operating modes including; multiplier, multiplier-accumulator, multiplier-adder/subtractor, three input adder, barrel shifter, wide bus multiplexers, or wide counters.
• Cascade DSP Slices without using FPGA fabric or routing resources to perform wide math functions, DSP filters, and complex arithmetic.

• 18-bit by 18-bit, two's complement multiplier with full precision 36-bit result, sign extended to 48 bits.
• Three input, flexible 48-bit adder/subtracter with optional registered accumulation feedback.
• Over 40 dynamic user-controller operating modes to adapt XtremeDSP slice functions from clock cycle to clock cycle.
• Cascading, 18-bit B bus, supporting input sample propagation.
• Cascading, 48-bit P bus, supporting output propagation of partial results.
• Multi-precision multiplier and arithmetic support with 17-bit operand right shift to align wide multiplier partial products (parallel or sequential multiplication).
• Symmetric intelligent rounding support for greater computational accuracy.
• Performance-enhancing pipeline options for control and data signals are selectable by configuration bits.
• Input port "C" typically used for multiply, add, large three-operand addition or flexible rounding mode.
• Separate reset and clock enable for control and data registers

Protect your intellectual property with security you can bank on. Virtex™-4 FPGAs protect your design with AES (Advanced Encryption Standard) technology-the same technology used by financial institutions worldwide.

Features at a Glance

• Software-based bitstream encryption and on-chip bitstream decryption logic with dedicated memory for storing the 256-bit encryption key.
• You generate the encryption key and encrypted bitstream using Xilinx ISE™ software. During configuration, the Virtex-4 device decrypts the incoming bitstream.

Battery-backed key provides unbreakable security

The Xilinx approach to security makes it virtually impossible for thieves to steal your design data. Virtex-4 FPGAs store the encryption key internally in dedicated RAM, backed up by a small externally connected battery (typical life 20+ years). It is not possible to read the encryption key out of the device. In contrast to protection schemes that use non-volatile key storage, any attempt to remove the Virtex-4 FPGA from the board in order to decapsulate the package for probing results in the instant loss of your encryption key and programming data.

Designing with Secure Chip AES

• Encrypt your design data with the iMPACT configuration tools included in ISE software