• Highest bandwidth FPGA offers a low-risk path to quickly prototype and bring to production robust 40G and 100G applications for bridging, switching, and aggregation in networking, telecom, and imaging
• Single-FPGA solution for 100GE MAC and 100GE-to-Interlaken bridging
• Single-FPGA solution for 40G transponders/muxponders
• Efficient implementation of 100G transponders/muxponders with FEC
• Enables integration of advance functionality such as packet processing, encryption, and traffic management
• Up to 24 GTH multi-rate transceivers supporting line rates above 11Gbps for connecting to x10G, 40G and 100G networks
• Up to 48 GTX multi-rate transceivers supporting up to 6.6Gbps enable reliable interfaces to legacy ASICs, ASSPs, and backplanes

• Build efficient, robust links to x10G, 40G, and 100G Ethernet networks with transceivers supporting line rates from 9.953 Gbps to 11.18 Gbps
• Up to 24 GTH transceivers in a single Virtex-6 HXT FPGA
• Low power consumption: 220mW (typ) at 10.3125 Gbps
• Achieve signal integrity required for chip-to-chip, chip-to-optics, and 10G backplane applications with built-in Tx pre-emphasis, Rx linear equalization, and Rx DFE
• Sophisticated adaptive equalization engine for ease of use
• Obtain assured compliance with popular standards such as 10/40/100G Ethernet, OTU-2/4, OC-192, and SFP+
• Integrated 64b/66b and 8b/10b coding support
• Simple and highly flexible clocking structure that enables multi-protocol designs

• Connect to legacy ASICs, ASSPs, and backplanes with transceivers supporting line rates from 150Mbps to 6.6Gbps
• 25% lower power consumption: <150mW (typ) at 6.6Gbps
• Up to 48 GTX transceivers in a single Virtex-6 HXT FPGA
• Highly flexible clocking enables independent Rx and Tx operation to effectively double the number of transceivers available for certain applications
• Obtain assured compliance with popular standards such as 10/40/100G Ethernet, PCI Express, OC-48, XAUI, SRIO, and HD-SDI
• Second-generation integrated PCI Express blocks and third-generation Tri-mode Ethernet MAC blocks make it easy to implement popular interfaces

Achieve 80% reduction in PHY power and reduce system cost for packet processing systems.

• Reach higher performance and bandwidth within existing power and cooling footprints
• Integrate packet-processing and traffic-management functions with faster and wider data paths that satisfy tough throughput and latency requirements
• Up to 48 GTX transceivers providing flexible options for system-side interfaces: 6.25G, 5.0G, 4.25G, 3.125G
• Implement high-bandwidth data buffering with flexible SelectIO™ technology that simplifies interfacing to DDR3, RLDRAM, and QDR SRAM and imposes no banking restrictions
• Up to 32Mbits Block RAM for low-latency data buffering
• Implement 40G and 100G bridging with IP for key protocols and flexible serial transceivers supporting line rates above 11Gbps

Achieve 80% reduction in PHY power and reduce system cost for transport systems.

• Meet stringent OTU protocol jitter requirements with GTH transceivers
• Flexible clocking makes it easy to implement multiple independent clock domains
• Implement 40G and 100G bridging with IP for key protocols and flexible serial transceivers supporting 11.18Gbps line rates

Combine Virtex-6 FPGA and Spartan-6 FPGA families to build low cost IP-based equipment that bridges broadcast and telecommunications networks.

• Reduce cost per-channel by integrating interfaces, codecs, and video processing algorithms in high-capacity FPGAs that provide 48 GTX and 24 GTH transceivers
• Differentiate your system with improved video quality enabled by integrated DSP resources
• Aggregate multiple uncompressed SDI video streams up to full 1080p60 HD onto 10Gbps Ethernet networks, or bridge multiple compressed ASI streams onto 1Gbps Ethernet for triple play services using integrated low-power transceivers
• Accelerate implementation with reference designs for triple-rate SDI, audio mux/demux, and more