Virtex-6 FPGA Family
The Virtex®-6 FPGA family is the high-performance silicon foundation for Targeted Design Platforms. Consuming 50% lower power and delivering 20% lower cost than the previous generation, the new family is built with the right mix of programmability, integrated blocks for DSP, memory, and connectivity support - including high-speed transceiver capabilities - to satisfy the insatiable demand for higher bandwidth and higher performance.
Virtex-6 FPGA Family Benefits
- Achieve a one speed-grade performance gain with second-generation ExpressFabric technology, 600MHz clocking technology and performance-tuned IP blocks
- Build high-bandwidth interfaces for DDR3 memory with flexible SelectIO technology
- Accelerate DSP performance with DSP48E1 slices
- Advanced 40nm process, architecture, tools, and system level optimizations reduce core power by 30%
- Low-voltage option increases power savings by 50% without significant performance penalties
- Enhanced SelectIO technology reduces I/O power by up to 50%
- Choose between two varieties of low-power serial transceivers offering bandwidth in excess of 11Gbps
- Obtain assured compliance with popular standards such as 10/40/100G Ethernet, SFP+, OTU-1/2/4, PCI Express®, OC-48, XAUI, SRIO, and HD-SDI
- Implement widely-used interfaces with second-generation integrated PCI Express blocks and third-generation Tri-mode Ethernet MAC blocks
- Integrate multiple functions into a single PCIe®-enabled (Gen1 and Gen2) FPGA supporting x1, x2, x4, and x8
Virtex-6 FPGA Comparison Table
| Features | LXT | SXT | HXT |
|---|---|---|---|
| High-performance Logic | |||
| High-density ASIC prototyping logic | |||
| General purpose processing | |||
| Digital signal processing | |||
| Ultra-high performance digital signal processing | |||
| Low-power serial I/O | |||
| Serial I/O bandwidth |
Key Documents
| Name | File Size | Modified Date |
|---|---|---|
| WP420 - Xilinx Virtex-6/Spartan-6 FPGA DDR3 Signal Integrity Analysis and PCB Layout Guidelines | 2.22 MB | 06/26/2012 |
| Virtex-6 Family Overview | 383 KB | 01/19/2012 |
| WP310 - Addressing the Performance Bottleneck in Modern SoC Design – Serial I/O Connectivity | 1.75 MB | 09/15/2009 |
| WP298 - Power Consumption at 40 and 45 nm | 1.59 MB | 04/13/2009 |
| WP368 - Unlock New Levels of Productivity for Your Design Using ISE Design Suite 12 | 509 KB | 05/03/2010 |
| WP370 - Reducing Switching Power with Intelligent Clock Gating | 395 KB | 03/01/2011 |
| Virtex-6 Product Brief |